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19-0230; Rev 2a; 1/97
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
_______________General Description
The MAX536/MAX537 combine four 12-bit, voltage-output digital-to-analog converters (DACs) and four precision output amplifiers in a space-saving 16-pin package. Offset, gain, and linearity are factory calibrated to provide the MAX536's 1LSB total unadjusted error. The MAX537 operates with 5V supplies, while the MAX536 uses -5V and +12V to +15V supplies. Each DAC has a double-buffered input, organized as an input register followed by a DAC register. A 16-bit serial word is used to load data into each input/DAC register. The serial interface is compatible with either SPI/QSPITM or MicrowireTM, and allows the input and DAC registers to be updated independently or simultaneously with a single software command. The DAC registers can be simultaneously updated with a hardware LDAC pin. All logic inputs are TTL/CMOS compatible.
____________________________Features
o Four 12-Bit DACs with Output Buffers o Simultaneous or Independent Control of Four DACs via a 3-Wire Serial Interface o Power-On Reset o SPI/QSPI and Microwire Compatible o 1LSB Total Unadjusted Error (MAX536) o Full 12-Bit Performance without Adjustments o 5V Supply Operation (MAX537) o Double-Buffered Digital Inputs o Buffered Voltage Output o 16-Pin DIP/SO Packages
MAX536/MAX537
______________Ordering Information
PART MAX536ACPE MAX536BCPE MAX536ACWE MAX536BCWE MAX536BC/D MAX536AEPE MAX536BEPE MAX536AEWE MAX536BEWE MAX536AMDE MAX536BMDE TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 16 Ceramic SB** 16 Ceramic SB** (LSB) 12 1 12 1 1 12 1 12 1 12 1
INL
________________________Applications
Industrial Process Controls Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control Devices Remote Industrial Controls Microprocessor-Controlled Systems
________________Functional Diagram
SDO LDAC DECODE CONTROL INPUT REG A INPUT REG B INPUT REG C INPUT REG D SR CONTROL CS SCK REFCD DAC REG A DAC REG B DAC REG C DAC REG D VDD DGND VSS TP REFAB AGND
Ordering Information continued at end of data sheet. * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883.
__________________Pin Configuration
MAX536/MAX537
OUTA DAC A OUTB DAC B OUTC DAC C OUTD
OUTB 1 OUTA 2 VSS 3 AGND 4 REFAB 5 DGND 6 LDAC 7 SDI 8 16 OUTC 15 OUTD 14 VDD
TOP VIEW
16-BIT SHIFT REGISTER
MAX536 MAX537
13 TP 12 REFCD 11 SDO 10 SCK 9 CS
DAC D
SDI
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
ABSOLUTE MAXIMUM RATINGS
VDD to AGND or DGND MAX536 ..................................................................-0.3V, +17V MAX537 ....................................................................-0.3V, +7V VSS to AGND or DGND ...............................................-7V, +0.3V SDI, SCK , CS, LDAC, TP, SDO to AGND or DGND.....................................-0.3V, (VDD + 0.3V) REFAB, REFCD to AGND or DGND .............-0.3V, (VDD + 0.3V) OUT_ to AGND or DGND .............................................VDD, VSS Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) .................842mW Wide SO (derate 9.52mW/C above +70C).................762mW Ceramic SB (derate 10.53mW/C above +70C)..................842mW Operating Temperature Ranges MAX53_AC_E/BC_E.............................................0C to +70C MAX53_AE_E/BE_E ..........................................-40C to +85C MAX53_AMDE/BMDE .....................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX536
(VDD = +15V, VSS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Resolution SYMBOL N TA = +25C MAX536A MAX536B MAX536AC Total Unadjusted Error (Note 1) TUE TA = TMIN to TMAX MAX536BC MAX536AE MAX536BE MAX536AM MAX536BM Integral Nonlinearity Differential Nonlinearity INL DNL MAX536A MAX536B Guaranteed monotonic TA = +25C MAX536A MAX536B MAX536AC Offset Error TA = TMIN to TMAX MAX536BC MAX536AE MAX536BE MAX536AM MAX536BM RL = Gain Error VDD Power-Supply Rejection Ratio VSS Power-Supply Rejection Ratio 2 RL = 5k PSRR PSRR MAX536_C/E MAX536_M 0.02 0.03 -0.1 -0.6 0.15 CONDITIONS MIN 12 1.0 2.0 2.0 3.0 2.5 3.5 3.0 4.0 0.50 1 1 2.5 5.0 5.0 7.5 6.1 8.5 7.5 10.0 1.0 1.5 2.0 0.125 0.30 LSB/V LSB/V LSB mV LSB LSB LSB TYP MAX UNITS Bits
STATIC PERFORMANCE--ANALOG SECTION
TA = +25C, 10.8V < VDD < 16.5V TA = +25C, -5.5V < VSS < -4.5V
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX536 (continued)
(VDD = +15V, VSS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX536/MAX537
MATCHING PERFORMANCE (TA = +25C) Total Unadjusted Error Gain Error Offset Error Integral Nonlinearity REFERENCE INPUT Reference Input Range Reference Input Resistance Reference 3dB Bandwidth REF RREF Code dependent, minimum at code 555 hex VREF = 2Vp-p VREF = 10Vp-p at 400Hz VREF = 10Vp-p at 4kHz 0.0 5 700 -100 dB -82 0.012 % VDD - 4 V k kHz INL MAX536A MAX536B TUE MAX536A MAX536B 0.1 1.2 1.2 0.2 1.0 2.0 1.0 2.5 5.0 1.0 LSB LSB mV LSB
MULTIPLYING-MODE PERFORMANCE
Reference Feedthrough
Input code = all 0s
Total Harmonic Distortion Plus Noise
THD + N
VREF = 2.0Vp-p at 50kHz
DIGITAL INPUTS (SDI, SCK, CS, LDAC) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance (Note 2) DIGITAL OUTPUT (SDO) Output Low Voltage Output Leakage Current VOL SDO sinking 5mA SDO = 0V to VDD 5 To 12LSB of full scale VREF = 5V VDD VSS IDD ISS TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX -6 10.8 -4.5 8 3 5 8 0.18 0.40 10 V A V/s s nV-s nV-s VIH VIL VIN = 0V or VDD 2.4 0.8 1.0 10 V V A pF
DYNAMIC PERFORMANCE (RL = 5k, CL = 100pF) Voltage-Output Slew Rate Output Settling Time Digital Feedthrough Digital Crosstalk (Note 3) POWER SUPPLIES Positive Supply Range Negative Supply Range Positive Supply Current (Note 4) Negative Supply Current (Note 4) 16.5 -5.5 18 25 -16 -23 V V mA mA
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
ELECTRICAL CHARACTERISTICS--MAX536 (continued)
(VDD = +15V, VSS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Internal Power-On Reset Pulse Width (Note 2) SCK Clock Period SCK Pulse Width High SCK Pulse Width Low CS Fall to SCK Rise Setup Time SCK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCK Rise to SDO Valid Propagation Delay (Note 6) SCK Fall to SDO Valid Propagation Delay (Note 7) CS Fall to SDO Enable (Note 8) CS Rise to SDO Disable (Note 9) SCK Rise to CS Fall Delay CS Rise to SCK Rise Hold Time LDAC Pulse Width Low CS Pulse Width High Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Note 5) tPOR tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tDV tTR tCS0 tCS1 tLDAC tCSW Continuous SCK, SCK edge ignored SCK edge ignored 20 20 30 40 1k pull-up on SDO to VDD, CLOAD = 50pF 1k pull-up on SDO to VDD, CLOAD = 50pF SDO high SDO low SDO high SDO low 100 30 30 20 10 40 0 78 50 81 53 27 40 105 80 110 85 45 60 26 20 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TUE is specified with no resistive load. Guaranteed by design. Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly. All input signals are specified with tR = tF 5ns. Logic input swing is 0V to 5V. Serial data clocked out of SDO on SCK's falling edge. (SDO is an open-drain output for the MAX536. The MAX537's SDO pin has an internal active pull-up.) Note 7: Serial data clocked out of SDO on SCK's rising edge. Note 8: SDO changes from High-Z state to 90% of final value. Note 9: SDO rises 10% toward High-Z state.
4
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX537
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity SYMBOL N INL DNL MAX537A MAX537B Guaranteed monotonic TA = +25C MAX537A MAX537B MAX537AC Offset Error TA = TMIN to TMAX MAX537BC MAX537AE MAX537BE MAX537AM MAX537BM Gain Error VDD Power-Supply Rejection Ratio VSS Power-Supply Rejection Ratio Gain Error Offset Error Integral Nonlinearity REFERENCE INPUT Reference Input Range Reference Input Resistance Reference 3dB Bandwidth Reference Feedthrough Total Harmonic Distortion Plus Noise Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance (Note 2) REF RREF Code dependent, minimum at code 555 hex VREF = 2Vp-p Input code = all 0s VREF = 10Vp-p at 400Hz VREF = 10Vp-p at 4kHz THD + N VREF = 850mVp-p at 100kHz 0.0 5 700 -100 -82 0.024 % VDD - 2.2 V k kHz dB INL MAX537A MAX537B PSRR PSRR RL = RL = 5k TA = +25C, 4.5V VDD 5.5V TA = +25C, -5.5V VSS -4.5V -0.3 -0.8 0.01 0.02 CONDITIONS MIN 12 0.15 0.50 1 1 3.0 6.0 6.0 9.0 7.0 11.0 9.0 15.0 1.5 3.0 0.5 0.7 LSB LSB/V LSB/V mV TYP MAX UNITS Bits LSB LSB
MAX536/MAX537
STATIC PERFORMANCE--ANALOG SECTION
MATCHING PERFORMANCE (TA = +25C) 0.1 0.3 0.3 0.35 1.25 3.0 6.0 1.0 LSB mV LSB
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUTS (SDI, SCK, CS, LDAC) VIH VIL VIN = 0V or VDD 2.4 0.8 1.0 10 V V A pF
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5
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
ELECTRICAL CHARACTERISTICS--MAX537 (continued)
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DIGITAL OUTPUT (SDO) Output High Voltage Output Low Voltage Voltage-Output Slew Rate Output Settling Time Digital Feedthrough Digital Crosstalk (Note 3) POWER SUPPLIES Positive Supply Range Negative Supply Range Positive Supply Current (Note 4) Negative Supply Current (Note 4) VDD VSS IDD ISS TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX -4.7 4.5 -4.5 5.5 5.5 -5.5 12 16 -10 -14 V V mA mA To 12LSB of full scale VOH VOL SDO sourcing 2mA SDO sinking 2mA VDD - 0.5 VDD - 0.25 0.13 5 5 5 5 0.40 V V V/s s nV-s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (RL = 5k, CL = 100pF)
TIMING CHARACTERISTICS (Note 5) Internal Power-On Reset Pulse Width (Note 2) SCK Clock Period SCK Pulse Width High SCK Pulse Width Low CS Fall to SCK Rise Setup Time SCK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCK Rise to SDO Valid Propagation Delay (Note 6) SCK Fall to SDO Valid Propagation Delay (Note 7) tPOR tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 CLOAD = 50pF CLOAD = 50pF MAX537_C/E MAX537_M MAX537_C/E MAX537_M 123 MAX537_C/E MAX537_M MAX537_C/E MAX537_M MAX537_C/E MAX537_M MAX537_C/E MAX537_M 100 35 40 35 40 40 50 0 40 50 0 116 200 230 210 250 24 50 s ns ns ns ns ns ns ns ns ns
6
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
ELECTRICAL CHARACTERISTICS--MAX537 (continued)
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CS Fall to SDO Enable CS Rise to SDO Disable (Note 10) SCK Rise to CS Fall Delay CS Rise to SCK Rise Hold Time LDAC Pulse Width High CS Pulse Width High Note 2: Note 3: Note 4: Note 5: Note 6: SYMBOL tDV tTR tCS0 tCS1 tLDAC tCSW CLOAD = 50pF CLOAD = 50pF Continuous SCK, SCK edge ignored SCK edge ignored MAX537_C/E MAX537_M MAX537_C/E MAX537_M CONDITIONS MAX537_C/E MAX537_M MAX537_C/E MAX537_M MAX537_C/E MAX537_M MAX537_C/E MAX537_M 35 40 35 40 50 70 100 125 70 MIN TYP 75 MAX 140 170 130 165 UNITS ns ns ns ns ns ns
Guaranteed by design. Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly. All input signals are specified with tR = tF 5ns. Logic input swing is 0V to 5V. Serial data clocked out of SDO on SCK's falling edge. (SDO is an open-drain output for the MAX536. The MAX537's SDO pin has an internal active pull-up.) Note 7: Serial data clocked out of SDO on SCK's rising edge. Note 10: When disabled, SDO is internally pulled high.
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7
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX536 INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE
MAX536/7-01
MAX536
MAX536 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX536/7-02
MAX536 TOTAL HARMONIC DISTORTION PLUS NOISE vs. REFERENCE FREQUENCY
0.175 0.150 THD + NOISE (%) 0.125 0.100 0.075 0.050 RL = NO LOAD, CL = 0pF DAC CODE = ALL 1s REFAB = 10Vp-p RL = 10k, CL = 100pF
MAX1536/7-03
1.0 VSS = -5V 0.6 INL ERROR (LSB) VDD = +15V
20 10 RELATIVE OUTPUT (dB) 0 -10 -20 -30 -40
REFAB SWEPT 2Vp-p VOUTA MONITORED
0.200
0.2
-0.2
VDD = +12V
--0.6
0.025 0 1k 10k 100k FREQUENCY (Hz) 1M 10M 10 FREQUENCY (kHz) 100 200
-1.0 0 4 8 12 REFERENCE VOLTAGE (V) 16
-50
MAX536 TOTAL HARMONIC DISTORTION PLUS NOISE vs. REFERENCE FREQUENCY
MAX1536/7-03b
MAX536 FULL-SCALE ERROR vs. LOAD
MAX536/7-04
MAX536 SUPPLY CURRENT vs. TEMPERATURE
MAX536/7-05
0.200 0.175 0.150 THD + NOISE (%) 0.125 0.100 0.075 0.050 0.025 0 10 FREQUENCY (kHz) 100 RL = NO LOAD, CL = 0pF RL = 10k, CL = 100pF DAC CODE = ALL 1s REFAB = 5Vp-p
1 0 FULL-SCALE ERROR (LSB) -1 -2 -3 -4 -5
10
6 SUPPLY CURRENT (mA) VDD = +15V VSS = -5V
IDD
2
-2 ISS -6
-10 0.1 1 10 LOAD (k) 100 1000 -60 -20 20 60 100 140 TEMPERATURE (C)
200
MAX536 REFERENCE FEEDTHROUGH AT 400Hz
MAX536 REFERENCE FEEDTHROUGH AT 4kHz
REFAB, 5V/div 0V
REFAB, 5V/div 0V
OUTA, 100V/div
OUTA, 200V/div
500s/div INPUT CODE = ALL 0s INPUT CODE = ALL 0s
50s/div
8
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX536/MAX537
MAX536
MAX536 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
MAX536 NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF)
CS, 5V/div
CS, 5V/div
OUTA, 5V/div OUTA, 2V/div
OUTA, 5mV/div
5s/div VDD = +15V, VSS = -5V, REFAB = 5V, CL = 100pF, RL = 10k
1s/div VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10k
MAX536 POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON)
MAX536 DIGITAL FEEDTHROUGH
CS, 5V/div OUTA, 5V/div
SCK, 5V/div
OUTA, -10V OFFSET 5mV/div
OUTA, AC-COUPLED, 10mV/div
1s/div VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10k VDD = +15V, VSS = -5V, REFAB = 10V, CS = HIGH, DIN TOGGLING AT 12 THE CLOCK RATE, OUTA = 5V
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9
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX537 INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE
MAX536/7-06
MAX537
MAX537 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX536/7-07
MAX537 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
REFAB = 2.5Vp-p 0.175 0.150 THD + NOISE (%) 0.125 0.100 0.075 RL = NO LOAD, CL = 0pF 0.050 0.025 RL = 10k, CL = 100pF
MAX1536/7-14
2.0 1.5 1.0 INL ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 1 2 VREF (V) 3 4 5 VDD = +5V VSS = -5V
20 10 RELATIVE OUTPUT (dB) 0 -10 -20 -30 -40 -50 1k
REFAB SWEPT 2Vp-p VOUTA MONITORED
0.200
10k
100k FREQUENCY (Hz)
1M
10M
0 10 FREQUENCY (kHz) 100 200
MAX537 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX1536/7-09
MAX537 FULL-SCALE ERROR vs. LOAD
MAX536/7-10
MAX537 SUPPLY CURRENT vs. TEMPERATURE
MAX536/7-11
0.200 0.175 0.150 THD + NOISE (%) 0.125 0.100 RL = 10k, CL = 100pF 0.075 0.050 0.025 RL = NO LOAD, CL = 0pF 0 10 FREQUENCY (kHz) 100 REFAB = 1Vp-p
2 1 FULL-SCALE ERROR (LSB) 0 -1 -2 -3 -4
5
3 SUPPLY CURRENT (mA) VDD = +5V VSS = -5V
IDD
1
-1 ISS -3
-5 0.1 1 10 LOAD (k) 100 1000 -60 -20 20 60 100 140 TEMPERATURE (C)
200
MAX537 REFERENCE FEEDTHROUGH AT 400Hz
MAX537 REFERENCE FEEDTHROUGH AT 4kHz
REFAB, 1V/div 0V
REFAB, 1V/div 0V
OUTA, AC-COUPLED, 100V/div
OUTA, AC-COUPLED, 100V/div
500s/div INPUT CODE = ALL 0s INPUT CODE = ALL 0s
50s/div
10
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX536/MAX537
MAX537
MAX537 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) MAX537 NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF)
CS, 5V/div
CS, 5V/div
OUTA, 1V/div
OUTA, 5mV/div
5s/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10k
1s/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10k
MAX537 POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON)
MAX537 DIGITAL FEEDTHROUGH
CS, 5V/div
SCK, 5V/div
OUTA, 5mV/div
OUTA, AC-COUPLED, 20mV/div
1s/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10k
100ns/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CS = HIGH, DIN TOGGLING AT 12 THE CLOCK RATE, OUTA = 1.25V
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11
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME OUTB OUTA VSS AGND REFAB DGND LDAC SDI CS SCK SDO REFCD TP VDD OUTD OUTC DAC B Output Voltage DAC A Output Voltage Negative Power Supply Analog Ground Reference Voltage Input for DAC A and DAC B Digital Ground Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input registers to their respective DAC registers. Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge. Chip-Select Input (active low). A low level on CS enables the input shift register and SDO. On CS's rising edge, data is latched into the appropriate register(s). Shift Register Clock Input Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low. For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pull-up to VDD. Reference Voltage Input for DAC C and DAC D Test Pin. Connect to VDD for proper operation. Positive Power Supply DAC D Output Voltage DAC C Output Voltage FUNCTION
_______________Detailed Description
The MAX536/MAX537 contain four 12-bit voltage-output DACs that are easily addressed using a simple 3-wire serial interface. They include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see the Functional Diagram on the front page). The DACs are "inverted" R-2R ladder networks that convert 12-bit digital inputs into equivalent analog output voltages in proportion to the applied reference-voltage inputs. DAC A and DAC B share the REFAB reference input, while DAC C and DAC D share the REFCD reference input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs.
R R R VOUT
2R
2R D0
2R D9
2R D10
2R D11
REF AGND
SHOWN FOR ALL 1s ON DAC
Reference Inputs
The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for its two corresponding DACs. The REFAB/REFCD voltage range is 0V to (VDD - 4V) for the MAX536 and 0V to (VDD - 2.2V) for the MAX537. The output voltages VOUT_ are represented by
12
Figure 1. Simplified DAC Circuit Diagram
a digitally programmable voltage source as: VOUT_ = NB (VREF) / 4096 where NB is the numeric value of the DAC's binary input code (0 to 4095) and VREF is the reference voltage.
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
The input impedance at each reference input is code dependent, ranging from a low value of typically 6k (with an input code of 0101 0101 0101) to a high value of 60k (with an input code of 0000 0000 0000). Since the input impedance at the reference pins is code dependent, load regulation of the reference source is important. The REFAB and REFCD reference inputs have a 5k guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance becomes 2.5k. A voltage reference with a load regulation of 0.001%/mA, such as the MAX674, would typically deviate by 0.164LSB (0.328LSB worst case) when simultaneously driving both MAX536 reference inputs at 10V. An op amp, such as the MAX400 or OP07, can be used to buffer the reference to increase reference accuracy. The op amp's closed-loop output impedance should be kept below 0.05 to ensure an error of less than 0.08LSB. Reference accuracy is also improved by driving the REFAB and REFCD pins separately, or by using a reference with excellent accuracy and superior load regulation, such as the MAX676/MAX677/MAX678. The reference input capacitance is also code dependent and typically ranges from 125pF to 300pF.
Output Buffer Amplifiers
All MAX536/MAX537 voltage outputs are internally buffered by precision unity-gain followers with a typical slew rate of 5V/s for the MAX536 and 3V/s for the MAX537. With a full-scale transition at the MAX536 output (0V to 10V or 10V to 0V), the typical settling time to 1/2LSB is 3s when loaded with 5k in parallel with 100pF (loads less than 5k degrade performance). With a full-scale transition at the MAX537 output (0V to 2.5V or 2.5V to 0V), the typical settling time to 1/2LSB is 5s when loaded with 5k in parallel with 100pF (loads less than 5k degrade performance). Output dynamic responses and settling performances of the MAX536/MAX537 output amplifier are shown in the Typical Operating Characteristics.
MAX536/MAX537
Serial-Interface Configurations
The MAX536/MAX537's 3-wire or 4-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied either high or low for a 3-wire interface, or used as the fourth input with a 4-wire interface. The connection between SDO and the serial-interface port is not necessary, but may be used for data echo. (Data held in the shift register
5V 5V RP SCK 1k SDO* SK SDI SDI SO MOSI RP 1k MISO* SS
MAX536 MAX537
SDO*
SI*
MICROWIRE PORT
MAX536 MAX537
SCK
SCK
SPI/QSPI PORT
CS CS I/O LDAC** LDAC** I/O
I/O
I/O CPOL = 0, CPHA = 0
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. THE MAX537 HAS AN INTERNAL ACTIVE PULL-UP TO VDD, SO RP IS NOT NECESSARY.
*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. THE MAX537 HAS AN INTERNAL ACTIVE PULL-UP TO VDD, SO RP IS NOT NECESSARY.
Figure 2. Connections for Microwire
Figure 3. Connections for SPI/QSPI
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
CS COMMAND EXECUTED
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD)
, , ,, , , ,,
SCK 1 8 9 16 SDI D15 D14 D13.......... MSB ..........D2 D1 D0 LSB SDO Q15.......... ...........Q0 MSB FROM PREVIOUS WRITE LSB FROM PREVIOUS WRITE CS INPUT REGISTER(S) UPDATED SCK 1 8 9 16 SDI D15 D14 D13 .......... MSB .......... D2 D1 D0 LSB SDO Q15.......... .......... Q0 MSB FROM PREVIOUS WRITE LDAC DACs UPDATED LSB FROM PREVIOUS WRITE
Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC
CS tCSO SCK tDS SDI tDV SDO tDO1 tDO2 tTR tDH tCSS tCL tCH tCP tCSH tCSI
tCSW
LDAC* *USE OF LDAC IS OPTIONAL
tLDAC
Figure 6. Detailed Serial-Interface Timing Diagram
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
of the MAX536/MAX537 can be shifted out of SDO and returned to the microprocessor for data verification; data in the MAX536/MAX537 input/DAC registers cannot be read.) With a 3-wire interface (CS, SCK, SDI) and LDAC tied high, the DACs are double-buffered. In this mode, depending on the command issued through the serial interface, the input register(s) may be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers may be simultaneously updated from the input registers. With a 3wire interface (CS, SCK, SDI) and LDAC tied low (Figure 4), the DAC registers remain transparent. Any time an input register is updated, the change appears at the DAC output with the rising edge of CS. The 4-wire interface (CS, SCK, SDI, LDAC) is similar to the 3-wire interface with LDAC tied high, except LDAC is a hardware input that simultaneously and asynchronously loads all DAC registers from their respective input registers when driven low (Figure 5). clocked into the internal shift register via the serial data input pin (SDI) on SCK's rising edge. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate MAX536/MAX537 input/DAC registers on CS's rising edge. Interface timing is optimized when serial data is clocked out of the microcontroller/microprocessor on one clock edge and clocked into the MAX536/MAX537 on the other edge. Table 1 lists the serial-interface programming commands. For certain commands, the 12 data bits are "don't cares". The programming command Load-All-DACs-From-ShiftRegister allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The NOP (no operation) command allows the register contents to be unaffected and is useful when the MAX536/MAX537 are configured in a daisy-chain (see the Daisy-Chaining Devices section). The command to change the clock edge on which serial data is shifted out of the MAX536/MAX537 SDO pin also loads data from all input registers to their respective DAC registers.
MAX536/MAX537
Serial-Interface Description
The MAX536/MAX537 require 16 bits of serial data. Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0), two control bits (C1, C0), and the 12 data bits D11...D0 (Figure 7). The 4-bit address/control code determines the following: 1) the register(s) to be updated and/or the status of the input and DAC registers (i.e., whether they are in transparent or latch mode), and 2) the edge on which data is clocked out of SDO.
MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits A1 A0 Control Bits C1 C0 Data Bits MSB.............................................LSB D11................................................D0 12 Data Bits
Serial-Data Output
The serial-data output, SDO, is the internal shift register's output. The MAX536/MAX537 can be programmed so that data is clocked out of SDO on SCK's rising (Mode 1) or falling (Mode 0) edge . In Mode 0, output data at SDO lags input data at SDI by 16.5 clock cycles, maintaining compatibility with Microwire, SPI/QSPI, and other serial interfaces. In Mode 1, output data lags input data by 16 clock cycles. On power-up, SDO defaults to Mode 1 timing. For the MAX536, SDO is an open-drain output that should be pulled up to +5V. The data sheet timing specifications for SDO use a 1k pull-up resistor. For the MAX537, SDO is a complementary output and does not require an external pull-up.
Test Pin
The test pin (TP) is used for pre-production analysis of the IC. Connect TP to VDD for proper MAX536/MAX537 operation. Failure to do so affects DAC operation.
4 Address/ Control Bits
Daisy-Chaining Devices
Any number of MAX536/MAX537s can be daisy-chained by connecting the SDO pin of one device (with a pull-up resistor, if appropriate) to the SDI pin of the following device in the chain (Figure 8). Since the MAX537's SDO pin has an internal active pull-up, the SDO sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the serial data out V OH and V OL specifications in the Electrical Characteristics.
Figure 7. Serial-Data Format (MSB Sent First)
Figure 6 shows the serial-interface timing requirements. The chip-select pin (CS) must be low to enable the DAC's serial interface. When CS is high, the interface control circuitry is disabled and the serial data output pin (SDO) is driven high (MAX537) or is a high-impedance open drain (MAX536). CS must go low at least tCSS before the rising serial clock (SCK) edge to properly clock in the first bit. When CS is low, data is
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD A1 0 0 1 1 0 0 1 1 X X 0 1 A0 0 1 0 1 0 1 0 1 0 1 X 1 C1 0 0 0 0 1 1 1 1 0 0 1 1 C0 1 1 1 1 1 1 1 1 0 0 0 0 D11...D0 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX LDAC 1 1 1 1 1 1 1 1 X X 1 X FUNCTION Load DAC A input register; DAC output unchanged. Load DAC B input register; DAC output unchanged. Load DAC C input register; DAC output unchanged. Load DAC D input register; DAC output unchanged. Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. Load all DACs from shift register. No operation (NOP) Update all DACs from their respective input registers. Mode 1 (default condition at power-up), DOUT clocked out on SCK's rising edge. All DACs updated from their respective input registers. Mode 0, DOUT clocked out on SCK's falling edge. All DACs updated from their respective input registers. Load DAC A input register; DAC A is immediately updated. Load DAC B input register; DAC B is immediately updated. Load DAC C input register; DAC C is immediately updated. Load DAC D input register; DAC D is immediately updated.
1 0 0 1 1
0 0 1 0 1
1 X X X X
0 1 1 1 1
XXXXXXXXXXXX 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data
X 0 0 0 0
"X" = Don't Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high, the DAC registers are latched.
When daisy-chaining MAX536s, the delay from CS low to SCK high (tCSS) must be the greater of: tDV + tDS or tTR + tRC + tDS - tCSW where tRC is the time constant of the external pull-up resistor (Rp) and the load capacitance (C) at SDO. For tRC < 20ns, tCSS is simply tDV + tDS. Calculate tRC from the following equation: VPULL-UP tRC = Rp (C) ln VPULL-UP - 2.4V
Additionally, when daisy-chaining devices, the maximum clock frequency is limited to: 1 fSCK(max) = ---------------------------- 2 (tDO + tRC - 38ns + tDS) For example, with t RC = 23ns (5V 10% supply with Rp = 1k and C = 30pF), the maximum clock frequency is 8.7MHz. Figure 9 shows an alternate method of connecting several MAX536/MAX537s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
[(
)]
where VPULL-UP is the voltage to which the pull-up resistor is connected.
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
+5V +5V +5V
RP* 1k
RP* 1k
RP* 1k
MAX536
SCK DIN CS SCK MAX537 SDI CS SDO SDI CS
MAX536
SCK MAX537 SDO SDI CS
MAX536
SCK MAX537 SDO
TO OTHER SERIAL DEVICES
* THE MAX537 HAS AN ACTIVE INTERNAL PULL-UP, SO RP IS NOT NECESSARY.
Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface
DIN SCK LDAC CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS LDAC
CS LDAC
CS LDAC
MAX536
SCK MAX537 SDI
MAX536
SCK MAX537 SDI
MAX536
SCK MAX537 SDI
Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3... are driven separately, thus controlling which data are written to devices 1, 2, 3...
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
__________Applications Information
Interfacing to the M68HC11*
PORT D of the 68HC11 supports SPI. The four registers used for SPI operation are the Serial Peripheral Control Register, the Serial Peripheral Status Register, the Serial Peripheral Data I/O Register, and PORT D's Data Direction Register. These registers have a default starting location of $1000. On reset, the PORT D register (memory location $1008) is cleared and bits 5-0 are configured as general-purpose inputs. Setting bit 6 (SPE) of the Serial Peripheral Control Register (SPCR) configures PORT D for SPI as follows:
BIT 7 6 NAME - - 5 SS 4 3 2 1 TXD 0 RXD
Bits 6 and 7 are not used. Writes to these bits are ignored. The PORT D Data Direction Register (DDRD) determines whether the port bits are inputs or outputs. Its configuration is shown below:
BIT 7 6 NAME - - 5 4 3 2 1 0
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
Setting DDD_ = 0 configures the port bit as an input, while setting DDD_ = 1 configures the port bit as an output. Writes to bits 6 and 7 have no effect. In SPI mode with MSTR = 1, when a PORT D bit is expected to be an input (SS, MISO, RXD), the corresponding DDRD bit (DDD_) is ignored. If the bit is expected to be an output (SCK, MOSI, TXD), the corresponding DDRD bit must be set for the bit to be an output.
SCK MOSI MISO
Table 2. Serial Peripheral Control-Register Definitions
NAME SPIE DEFINITION Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral Status Register's SPIF bit or MODF bit is set. Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a generalpurpose I/O port. When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary. Master/Slave select option Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the clock idles low. Determines the clock phase. SPI Clock-Rate Select SPR1 SPR1/0 0 0 1 1 SPR0 0 1 0 1 P clock divided by 2 P clock divided by 4 P clock divided by 16 P clock divided by 32
SPE DWOM MSTR CPOL CPHA
Table 3. Serial Peripheral Status-Register Definitions
NAME SPIF WCOL MODF DEFINITION SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR. The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by reading the SPSR and then accessing the SPDR. The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the "master" controller has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
Table 4. M68HC11 Programming Code
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
SS is an input intended for use in a multimaster environment. However, SS or unused PORT D bit RXD, TXD, or possibly MISO (if DAC readback is not used) should be configured as a general-purpose output and used as CS by setting the appropriate Data Direction Register bit. The SPCR configuration (memory location $1028) is shown below:
BIT 7 6 5 4 3 2 1 0
Unipolar Output
For a unipolar output, the output voltages and the reference inputs are the same polarity. Figure 10 shows the MAX536/MAX537 unipolar output circuit, which is also the typical operating circuit. Table 5 lists the unipolar output codes.
Bipolar Output
The MAX536/MAX537 outputs can be configured for bipolar operation using Figure 11's circuit. One op amp and two resistors are required per DAC. With R1 = R2: VOUT = VREF [(2NB / 4096) - 1] where N B is the numeric value of the DAC's binary input code. Table 6 shows digital codes and corresponding output voltages for Figure 11's circuit.
NAME SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 SETTING AFTER RESET 0 0 0 0 0 1 U* U*
SETTING FOR TYPICAL SPI COMMUNICATION 1** 0 1 0 1 0 0 0**
*U = Unknown **Depends on P clock frequency.
Table 5. Unipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 1111 ANALOG OUTPUT 4095 +VREF ( ------ ) 4096 2049 +VREF ( ------ ) 4096 2048 +VREF +VREF ( ------ ) = -------- 4096 2 2047 +VREF ( ------ ) 4096 1 +VREF ( ------ ) 4096 0V
Always configure the 68HC11 as the "master" controller and the MAX536/MAX537 as the "slave" device. When MSTR = 1 in the SPCR, a write to the Serial Peripheral Data I/O Register (SPDR), located at memory location $102A, initiates the transmission/reception of data. The data transfer is monitored and the appropriate flags are set in the Serial Peripheral Status Register (SPSR). The SPSR configuration is shown below:
BIT 7 6 NAME SPIF WCOL
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000 5 - 4 MODF 3 - 0 2 - 0 1 - 0 0 0000 - 0
0000 0000
0001 0000
RESET CONDITIONS 0 0 0 0
Table 6. Bipolar Code Table
DAC CONTENTS MSB LSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000
1 ) 4096
An example of 68HC11 programming code for a two-byte SPI transfer to the MAX536/MAX537 is given in Table 4. SS is used for CS, the high byte of MAX536/ MAX537 digital data is stored in memory location $0100, and the low byte is stored in memory location $0101.
ANALOG OUTPUT 2047 +VREF ( ------ ) 2048 1 +VREF ( ------ ) 2048 0V 1 -VREF ( ------ ) 2048 2047 -VREF ( ------ ) 2048 2048 -VREF ( ------ ) = -VREF 2048
Interfacing to Other Controllers
When using Microwire, refer to the section on Interfacing to the M68HC11 for guidance, since Microwire can be considered similar to SPI when CPOL = 0 and CPHA = 0. When interfacing to Intel's 80C51/80C31 microcontroller family, use bit-pushing to configure a desired port as the MAX536/MAX537 interface port. Bitpushing involves arbitrarily assigning I/O port bits as interface control lines, and then writing to the port each time a signal transition is required.
20
NOTE: 1LSB = (VREF) (
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
REFERENCE INPUTS +15V (+5V) 14 VDD 13 TP 2
MAX536 MAX537
5 REFAB DAC A
12 REFCD
MAX536 MAX537
R1 OUTA VREF +15V (+5V) R2
DAC B
1
OUTB VOUT
DAC C
16
DAC OUTPUT OUTC -5V
DAC D VSS 3 -5V NOTE: ( ) ARE FOR MAX537. AGND 4 DGND 6
15
R1 = R2 = 10k 0.1% OUTD
NOTES: ( ) ARE FOR MAX537. VREF IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537.
Figure 10. Unipolar Output Circuit
Figure 11. Bipolar Output Circuit
+15V (+5V) AC REFERENCE INPUT +4V (+750mV) 5 -4V (-750mV) 10k REFAB 13 TP 14 VDD 15k
+15V (+5V)
5 REFAB + VIN
13 TP
14 VDD
DAC B 1 OUTB
DAC A
2
OUTA
4
AGND VSS 3 -5V
MAX536/MAX537
DGND 6
MAX536/MAX537
VSS 3 -5V AGND 4 DGND 6
+
VBIAS
-
NOTES: ( ) ARE FOR MAX537. DIGITAL INPUTS NOT SHOWN.
NOTES: ( ) ARE FOR MAX537. DIGITAL INPUTS NOT SHOWN.
Figure 12. AC Reference Input Circuit
Figure 13. AGND Bias Circuit
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
Offsetting AGND
AGND can be biased from DGND to the reference voltage to provide an arbitrary nonzero output voltage for a zero input code (Figure 13). The output voltage VOUTA is:
3 VSS
VOUTA = VBIAS + NB (VIN) where VBIAS is the positive offset voltage (with respect to DGND) applied to AGND, and N B is the numeric value of the DAC's binary input code. Since AGND is common to all four DACs, all outputs will be offset by VBIAS in the same manner. As the voltage at AGND increases, the DAC's resolution decreases because its full-scale voltage swing is effectively reduced. AGND should not be biased more negative than DGND.
1N5817
MAX536 MAX537
4
AGND
Power-Supply Considerations
On power-up, VSS should come up first, VDD next, then REFAB or REFCD. If supply sequencing is not possible, tie an external Schottky diode between VSS and AGND as shown in Figure 14. On power-up, all input and DAC registers are cleared (set to zero code) and SDO is in Mode 0 (serial data is shifted out of SDO on the clock's rising edge). For rated MAX536 performance, VDD should be 4V higher than REFAB/REFCD and should be between 10.8V and 16.5V. When using the MAX537, VDD should be at least 2.2V higher than REFAB/REFCD and should be between 4.75V and 5.5V. Bypass both VDD and VSS with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible.
Figure 14. When VSS and VDD cannot be sequenced, tie a Schottky diode between VSS and AGND.
Using an AC Reference
In applications where the reference has AC signal components, the MAX536/MAX537 have multiplying capability within the reference input range specifications. Figure 12 shows a technique for applying a sine-wave signal to the reference input where the AC signal is offset before being applied to REFAB/REFCD. The reference voltage must never be more negative than DGND. The MAX536's total harmonic distortion plus noise (THD + N) is typically less than 0.012%, given a 5Vp-p signal swing and input frequencies up to 35kHz, or given a 2Vp-p swing and input frequencies up to 50kHz. The typical -3dB frequency is 700kHz as shown in the Typical Operating Characteristics graphs. For the MAX537, with an input signal amplitude of 0.85mVp-p, THD + N is typically less than 0.024% with a 5k load in parallel with 100pF and input frequencies up to 100kHz, or with a 2k load in parallel with 100pF and input frequencies up to 95kHz.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and DGND can create noise at the analog outputs. Tie AGND and DGND together at the DAC, then tie this point to the highest quality ground available. Good printed circuit board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Wire-wrapped boards are not recommended.
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
_Ordering Information (continued)
PART MAX537ACPE MAX537BCPE MAX537ACWE MAX537BCWE MAX537BC/D MAX537AEPE MAX537BEPE MAX537AEWE MAX537BEWE TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 16 Ceramic SB** 16 Ceramic SB** INL (LSB) 12 1 12 1 1 12 1 12 1 12 1
V SS
___________________Chip Topography
OUTA OUTB OUTC OUTD V DD
MAX536/MAX537
AGND
TP
REFAB
REFCD
MAX537AMDE -55C to +125C MAX537BMDE -55C to +125C
* Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883.
0.309" (7.848mm)
DGND SDO LDAC SCK
SDI CS 0.139" (3.5306mm)
TRANSISTOR COUNT: 5034 SUBSTRATE CONNECTED TO VDD
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537
________________________________________________________Package Information
PDIPN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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